It is becoming common for audio recording studios to digitize signals produced by analog sources, such as microphones. In these studios, audio recording, production, editing and processing is performed completely in the digital domain. For this reason, most modern digital audio equipment comes equipped to receive digital input signals and to provide digital output signals; analog-to-digital converters and digital-to-analog converters are often optional. There is, however, no established standard for digital sampling rates for all types of information. The need for simple digital interfacing between different equipment has thus become very important.
The most common solution to the digital interface problem is to use a phase-locked loop to recover the sample rate of input data, and to use the resulting high frequency clock as an internal system clock. One problem that often arises is that an internal system clock must be fixed at a frequency that is not related to the frequency of the input serial data. An example of this problem occurs in digital videotape recorders, where the internal system clock must be related to a standard video frequency, and must be able to lock up with a master video synchronizing generator whose frequency is not related to the frequency of serial input data, such as digital audio data. Therefore, such digital videotape recorders, and similar devices, need a sample rate converter to convert input audio signals sample at some unknown rate (though typically 44.1 kHz) to corresponding digital samples at a local, fixed sample rate.
There are two classes of sample rate converters: synchronous and asynchronous. In synchronous sample rate converters, an input sample rate is related to an output sample rate by a ratio of integers (3:2, for example), i.e., a rational number. While such a device is sometimes useful, the output rate is still related to the input rate. Equipment which uses this data still must lock to it.
Asynchronous sample rate converters, on the other hand, are designed to receive a stream of input data samples and produce output data samples when requested by the system (i.e., not necessarily at a fixed rate rationally related to the input rate). It is therefore capable of converting between any two sample rates, and the ratio of these rates may be irrational. Thus, the main purpose of an asynchronous digital sample rate converter is to decouple the sampling rate of the input and output data streams from the clock frequencies used in the processing or storage of these data streams. Further, an asynchronous converter may correctly follow the slow variations of the input and output sample rates. This type of sample rate converter is in the most commercial demand today.
A simple analog method to change from one sample rate to another is shown in FIG. 1. It uses a digital-to-analog (D/A) converter 50 followed by a brick wall filter 52 to convert the signal back to the analog domain. This analog signal from filter 52 is applied to an analog-to-digital (A/D) converter 54 which runs at a different sample rate. (See FIG. 1) This analog approach is complex and presents signal degradation problems, due to harmonic distortion and noise caused by the A/D and D/A converters. Thus, sample rate converters are more commonly implemented using digital interpolation filters.
The operation of a digital interpolation filter, in both the time and frequency domains, will now be described in connection with FIGS. 2A-2C.
In FIG. 2A digital data samples 40 are shown as a sample data signal x(N*T), sampled at a rate Fs=1/T. The Fourier transform of x(N*T) is X(w), which has periodic images 38 centered around all multiples of the sampling rate, as according to sampling theory.
A desired interpolation ratio (R) is chosen and, between each sample 40 of the original signal x(N*T), (R-1) zero-valued samples 42 are inserted at constant intervals, as shown in FIG. 2B. This operation does not alter the frequency-domain description of the signal, except that the signal is considered to be sampled at a rate of Fs.sub.-- new=R*Fs.
The signal which included the zero-valued samples is applied to a digital low-pass filter, with a cutoff frequency of one-half the input sample rate, as shown in FIG. 2c. The output of this filter is the desired interpolated signal, with images 44 around the higher sampling rate of Fs.sub.-- new.
Referring now to FIG. 3, a purely digital sample rate converter includes a digital interpolation filter 60 placed between input and output samplers 62 and 64, as shown in FIG. 3. The filter 60 includes a zero-stuff circuit 68 and a lowpass filter 70. A zero-order hold 66 is used at the output of the interpolation filter 60, otherwise sample times would never line up and the output would be zero.
The purpose of the digital interpolation filter 60 between the two input and output samplers 62 and 64 in FIG. 3 is to produce a stream of output samples on a much finer time grid than the original input samples. When these interpolated values are fed into the zero-order hold 66, then asynchronously re-sampled by the output sampler 64, the output values represent the "nearest" (in time) values produced by the interpolation filter. There is always some error in the output samples due to the fact that the output sampler 64 does not operate to request a sample at a time that exactly corresponds to a point on the fine time grid of the interpolated outputs. This error is inversely related to the interpolation ratio (R).
FIG. 4 shows a purely conceptual hardware implementation of a digital interpolation filter, referred to because of its conceptual simplicity, but which requires too much hardware to be implemented in a practical manner. The input signal is sampled by sampler 80. A number of zero-valued samples are inserted at constant intervals (defined by the interpolation ratio and the input sample rate) between each sample by a zero-value sample insertion circuit 82, and applied to an FIR interpolation filter 84 which is shown as a classic convolution machine employing a shift register 86 in which the value stored in each tap 88 is multiplied using multiplier 92 by a corresponding coefficient value (C.sub.0, C.sub.1, . . . , C.sub.n). These products are summed by adder 94 to form an output. The asynchronous output re-sampling switch 96 grabs the "nearest" interpolated output when it closes. The fact that the interpolated output is held in a register 98 for the duration of one cycle of the interpolation clock is what provides a zero-order-hold function.
With such a circuit, if the interpolation ratio is about 2.sup.16 (i.e., 65536) and the input sampling rate is 50 KHz, the shift register must operate at a rate of 3.27 GHz. Providing a clock signal at such a rate is highly impractical. Moreover, assuming that the shift register needs to be operated at a rate of 3.27 GHz and that a new interpolated output is produced on every cycle, the estimated length of a reasonably good 20 kHz low-pass filter, (operating at a sampling rate of 3.27 GHz, having less than 0.01 dB of ripple and attenuating by more than 110 dB any frequencies above 24 kHz), is about 4,194,304 taps. This number represents both the length of the shift register and the number of filter coefficients which must be stored.
To develop a practical implementation of a digital sample rate converter using a digital interpolation filter requires reducing this conceptual hardware model described above into a practical hardware implementation. That is, the number of taps and coefficients and the operating clock frequency must be reduced. While others have found solutions to these problems, these solutions are problematic and/or limited. Most are not suitable for implementation in an integrated circuit.
For example, one problem experienced by all currently known systems is that the input and output sample rates are expected to be fixed. Thus, these systems are inflexible to changes in the input and output sampling rates. Further, when these rates are changed, so that the filter changes from an interpolation filter to a decimation filter, or vice-versa, these systems require different hardware configurations. For an example, see U.S. Pat. Nos. 4,604,720 and 4,584,659, issued to Eduard Stikvoort and assigned to U.S. Philips Corporation. Changes in input or output sampling rates thus require user interaction to modify the sample rate converter, or even a different circuit, which is generally undesirable.
Solutions to the reduction of the conceptual hardware model of FIG. 4 are based on the fact that the number of non-zero data values that exist at any one time in the shift register 86 is equal to the number of taps divided by the interpolation ratio R. For the example given above, the number of non-zero values is 64. Thus, there is no reason to compute every interpolated output at the 3.27 GHz rate when only roughly one out of 65,536 outputs is used. Further, since filter convolution only needs to be performed when an output sample is required, occurring at the output sample rate, the required multiply/accumulate rate is the product of the output sample rate and the number of non-zero input data values in the shift register at any one time.
This method implies that the exact arrival time of an output sample request is measured, and that this information is used to determine where the non-zero data values are in the conceptual shift register. Once the locations of these values are determined, the correct subset of filter coefficients can also be determined. These coefficients and data values are multiplied and summed together to obtain the desired result. Thus, the zero value data need not be stored in the shift register at all. As long as the correct data values are maintained in the shift register, and the correct coefficient subset to use is determined, the correct output for a given output sample request can be determined. Thus, the process can be considered as a time-varying FIR filter. Depending on the relative phases of the input sample clock and the output sample clock, a particular set of 64 coefficients out of the total coefficient space would be chosen to compute any requested output.
The problem with this method is that the arrival of an output sample request needs to be accurately measured in order to determine the position of the non-zero data values in the shift register with no error, thus implying that a high frequency clock is available, for example, running at 3.27 GHz, which was to be avoided in the first place. The only solution to this problem is to effectively average many more coarse measurements in a way that the DC error is guaranteed to go to zero over the long term.
Another problem with reducing the conceptual model involves reducing the set of filter coefficients that must be stored. Some solutions have been proposed to this problem, such as in U.S. Pat. No. 4,825,398, issued to Andreas Koch, et al., and assigned to Willi Studer, AG. Although the linear interpolation method shown may reduce a set of four million stored filter coefficients to about 16,000, that amount of storage is still problematic for an integrated circuit implementation of a digital sample rate converter. Higher order (e.g. quadratic) interpolation may enable further reduction of this set, but increases computational complexity.
Other systems involve using a number of fixed prefilters in combination with a smaller variable filter. One problem with these circuits is that they require the use of a high-frequency clock signal which is related to the input rate. Thus, a phase-locked loop must be used, requiring analog components, which is undesirable for a purely digital integrated circuit implementation.
A number of U.S. patents have been cited in this section for background purposes. The disclosures of these patents (U.S. Pat. Nos. 4,584,659, 4,604,720 and 4,825,398) are hereby expressly incorporated by reference.